The present invention relates generally to signal generators and more particularly, to a signal generator utilizing a combination phased locked loop and frequency locked loop and having a frequency discriminator including a voltage tuned phase shifter wherein the frequency of the loop signal source is controlled by applying a tune voltage from the phase locked loop to the voltage controlled phase shifter.
Signal generators or frequency synthesizers utilizing a phase locked loop (PLL) to provide an output signal having a selectable, precise and stable frequency are well known in the art. Such a PLL includes a tunable oscillator, typically a voltage controlled oscillator (VCO) the output of which is locked to a known reference signal by means of a phase comparator. The phase comparator generates an output voltage or current that is proportional to the phase difference between the known reference signal and the VCO output signal. The output of the phase comparator is coupled back to the input of the VCO to tune the VCO to a desired frequency. This forces the VCO output signal to have the same frequency as the reference signal. By interposing a divide-by-N block between the output of the VCO and the phase comparator, the reference frequency may instead be compared with the VCO output frequency divided by N. The VCO output frequency will then be N times the reference signal frequency where N is an integer. Another technique known as fractional-N is utilized to generate signals having a frequency that is any rational multiple of the reference signal frequency. Such a technique is disclosed U.S. Pat. No. 3,928,813 issued to Charles A. Kingsford Smith on Dec. 23, 1975, entitled "Device For Synthesizing Frequencies Which Are Rational Multiples Of A Fundamental Frequency".
Typically most phased locked loop circuits are designed to exhibit a relatively wide bandwidth and will operate to minimize phase and frequency perturbations occurring at rates within the phase locked loop bandwidth. In applications requiring a frequency or phase modulated signal the phase locked loop will operate to eliminate any variations in the signal frequency caused by a modulation signal. Thus, it has become necessary to develop various circuit arrangements for satisfactorily phase or frequency modulating such phase locked systems. A typical approach to frequency modulating a phase locked loop system in effect combines two modulation paths, the first of which accommodates FM rates within the bandwidth of the phase locked loop and the second of which accommodates FM rates greater than the phased locked loop bandwidth. This approach may require that compensating circuitry be included to equalize the signal delay in the two modulation paths to provide satisfactory circuit operation and obtain linear, frequency modulation over a desired range of carrier frequencies.
Further, because of the phase noise generated by voltage controlled oscillators is typically substantially higher than that of frequency modulated oscillators employing high Q resonant networks (e.g., a resonant cavity) prior art frequency modulated PLLs do not satisfy the extremely low noise characteristics required by today's applications.
One approach to providing a low noise, frequency modulated signal source comprises a voltage controlled oscillator (VCO) having a first feedback path for establishing and maintaining phase lock of the VCO at the desired signal frequency and includes a second feedback path that reduces VCO phase noise by supplying negative feedback that is proportional to the VCO phase noise to the VCO frequency control terminal. This circuit arrangement is, in effect, a combined phase locked loop and frequency locked loop (FLL). Both types of feedback loops have been used to stabilize and reduce the phase noise produced by VCOs. The combination of the two loops provide lower noise and better frequency stability than could be had by using one or the other of the two loops alone. However, the frequency modulation problems associated with typical prior art phase locked loop frequency synthesizers are not overcome or alleviated by the combined PLL and FLL. Typically an FLL comprises a frequency discriminator, a loop amplifier filter and a VCO. The frequency discriminator comprises a power or signal splitter, a time delay network (e.g., a surface acoustical wave delay device, a resonant circuit or a coaxial cable), a phase shifting apparatus and a phase detector. Typically an RF power amplifier is included to provide adequate signal levels at the phase detector and to compensate for losses of the passive components. The power splitter provides two signal paths which are coupled to the inputs of the phase detector. Including the time delay network in one signal path and not the other provides a phase shift of the signal proportional to input frequency which is detected by comparing the signals on the two paths at the phase detector. Typically, an RF phase detector utilized in a frequency discriminator comprises a balanced mixer having an output voltage proportional to the cosine of the detected phase difference. Variable phase shifting apparatus included in one or both of the phase detector signal paths provides a phase offset such that the cosine of the phase difference at the phase detector output is near zero over the frequency range of interest. The output of the phase detector is coupled back to the frequency control terminal of the VCO with the proper polarity to reduce VCO frequency fluxuations to the point where the VCO is as stable as the frequency discriminator itself, within the FLL bandwidth. Thus, the frequency discriminator effectively tracks a phase locked loop frequency and, by properly configuring the network, a VCO output signal having low phase noise is attained without significantly altering the frequency selection characteristics. U.S. Pat. No. 4,336,505 entitled "Controlled Frequency Source Apparatus Including A Feedback Path For The Reduction of Phase Noise" issued to Donald G. Meyer on June 22, 1982, discloses a phase locked loop apparatus including a frequency locked loop to provide a low noise signal source having remote signal selection capabilities, a frequency range of one octave or more and less phase noise than prior art phase locked loop systems. Meyer describes a FLL of the type described hereinabove including a frequency discriminator having a feedback path from the phase detector to the variable phase shifting apparatus to maintain a phase detector output at zero volts, the optimum operating point. U.S. Pat. No. 4,321,706 entitled "Frequency Modulated Phase Locked Loop Signal Source" issued to Kingsley W. Craft on Mar. 23, 1982 discloses a low noise frequency modulated signal source of the general type disclosed by Meyer including circuitry that automatically adjusts the level of an applied modulation signal so that a given modulation signal provides a predetermined frequency deviation at the center frequency of each frequency subband over the desired frequency range. Frequency modulation (FM) is achieved by coupling a first modulation signal into the frequency discriminator phase detector output to be summed with the frequency locked loop feedback and is primarily effective at frequencies outside the effective phase locked loop bandwidth. A second modulation signal is coupled to a VCO which provides the phase locked loop reference signal to provide FM within the phase locked loop bandwidth. Circuitry is also included to prevent the FM signal from reaching portions of the phase noise reducing circuitry that maintains the average value of the frequency discriminator phase detector output signal substantially equal to zero at the desired carrier frequency.
Delay line discriminators having low noise, high sensitivity and wide bandwidth characteristics when used in a frequency locked loop will provide a VCO output signal having minimum phase noise. The delay line discriminator effectively demodulates the VCO output signal and supplies negative feedback which is proportional to the VCO phase noise. Since any FM on the VCO output signal will be seen as a noise signal by the delay line discriminator, FM will also be eliminated by the frequency locked loop. The amount of cancellation of the FM is dependent on the gain of the FLL and is limited by the FM noise floor of the frequency discriminator. A first order FLL includes an integration amplifier between the phase detector output and the VCO frequency control input. To prevent attenuation of the FM, the modulation signal must be applied prior to this integration amplifier in the FLL. When using a balanced mixer as a phase detector for the frequency discriminator, the optimum operating point of the phase detector is with the output voltage at approximately zero volts. At this point, the sensitivity to phase changes is the highest and rejection of amplitude modulation on the RF carrier is the greatest. This is also the most linear operating point for the phase detector which is important for low distortion FM of the VCO output signal. FM of the VCO output signal achieved by the summation of the FM signal at the discriminator phase detector output forces the phase detector operating voltage away from zero, thus reducing the sensitivity and the linearity of the phase detector.